锁相环

分析了该锁相环在移动通信中的应用并用C语言编写出移动通信输频软件。

Finally a software in C language for frequency-programming in mobile communication has been worked out .

基于相位噪声的锁相环IP核选择判据

The Selection Criterion of PLL IP Core Based on Jitter

调制器中采用预补偿的分数N锁相环。

A pre-compensation fractional-N phase-locked loop ( PLL ) is adopted in the modulator .

电压不对称情形下基于DSP软件锁相环的设计

Design and Realization of Software Phase-Locked Loop under Grid Voltage Dissymmetry

CPU控制的数字锁相环频率合成系统的FPGA实现

Realization of digital PLL frequency synthesizer with CPU controlling on FPGA

IC锁相环在脉冲占空比测量中的应用

Application of Integrated Circuit Phase-locked Loop in Measuring Pulse Duty Factor

一种采用新的相频检测技术的CMOS数字锁相环

A CMOS Digital PLL with a New Phase-frequency Detection Technique

X波段脉冲取样锁相环

X-band impulse governing oscillator

而且选用的FPGA内部还具有锁相环的逻辑单元，为本次设计带来了很大的方便。

And the choice has PLL internal FPGA logic modules for this design brings great convenience .

基于FPGA的高性能全数字锁相环设计与实现

FPGA-based high-performance all-digital phase-locked loop design

锁相环用CMOS鉴频鉴相器及电荷泵的实现

CMOS phase-frequency detector and charge pump design for PLL

电流模式CMOS高频集成锁相环

Current Mode High Frequency Integrated CMOS Phase locked Loop

基于DSP的在线式UPS锁相环设计

DSP-based Design of PLL For Online UPS

应用锁相环IC设计心率显示报警电路

Application of Phase Lock Loop IC to the Design of a Heart Rate Display and Alarm Circuit

一种低功耗射频CMOS电荷泵锁相环的设计

A Low-Power RF CMOS Charge Pump PLL

SEC中的全数字锁相环的分析及设计

Analysis and design of all digital phase-locked loops in SEC

锁相环在SDH网络中的应用

Application of PLL in Synchronous Digital Network over SDH

基于微波锁相环的Ka波段锁相信号源

Ka-band phase locked frequency source based on microwave phase locked loops

锁相环设计中采用差分调节的LC压控振荡器和全差分的电荷泵。

A differential tuned LC-VCO and a fully-differential charge pump are adopted in the PLL design .

锁相环行为级建模及在视频行锁相中的应用基于FPGA的三相锁相环的优化设计方案

Behavior Modeling of PLL and Its Application in Video Horizontal PLL Optimized implementation scheme of three phase phase-locked loop based on FPGA

设计了一种电压控制LC振荡器，利用LC振荡电路作为振荡源，通过变容二极管来调节振荡器的频率，采用锁相环来提高输出频率的稳定度，以FPGA+单片机作为整个系统的测控部分。

This paper presents a voltage-controlled LC oscillator with a phase-locked loop based on FPGA and MCU .

一种从E1信号中提取时钟的全数字锁相环

An All - Digital Phase Locked Loop for Clock Recovery from E1 Signal

锁相环（PLL）是当前实现时钟处理电路应用最为广泛的技术。

Phase-locked-loop ( PLL ) is currently the most wildly applied technique in CGU and CRC .

以应急光通信系统为工程背景，设计一种基于FPGA技术的嵌入式数字锁相环。

A embedded digital phase-locked logic ( DPLL ) is designed based on FPGA technology which used in the atmosphere laser communication system project .

用于光纤传输系统的CRC必须满足抖动要求。如果用简单的锁相环（PLL）来满足这一要求的话，将意味着非常窄的环路带宽和非常小的锁定范围。

Normally , a phase-locked loop has a very narrow loop bandwidth for good jitter attenuation .

重点研究了基于FPGA的全数字锁相环频率跟踪技术和数字化SPWM实现技术。

All Digital Phase-Locked Loop frequency tracking and digital SPWM realization technology based on FPGA are emphasized in the research .

第五章主要讲快速自适应锁相环的FPGA实现，通过仿真和测试的结果说明该自适应方法的优越性。

In the chapter 5 the FPGA implementation of fast-adaptive phase-locked loop is introduced and the superiority of the adaptive method through simulation is showed .

该VCO适于锁相环（PLL）用途。

The design is suitable for the usage in a phase-locked loop ( PLL ) .

并说明了该测量仪的多项关键技术，尤其是延时锁相环加RC延迟线的两级时间内插技术；

Some pivotal technologies of the instrument are described , especially the delay locked loop and RC delay line time interpolator techniques .

QPSK载波锁相环的鉴频辅助方法研究

Study of the Realization of QPSK Carrier Phase-locked Loop Aided by Frequency-detection