跳转指令

跳转指令可以控制PC的取值，直接寻找到目标地址；

Jump instruction can control the access value of PC , so the destination address can be got directly ;

ARM处理器每个异常中断对应一条跳转指令或者向PC寄存器赋值的数据访问指令。

Each exceptional interruption of ARM processor corresponds to a jump instruction or sends access instructions to the data evaluated by PC register .

为克服条件跳转指令的缺陷，新一代超长指令字（VLIW）体系结构的数字信号处理器（DSP）提供了对条件执行指令的支持。

As a conditional jump may cause significant code performance penalty , the architecture of recent VLIW DSPs offers support for conditional instructions .

不断挖掘指令级并行性（ILP）是提高处理器性能的关键，而分支跳转指令造成的控制相关，严重限制了ILP的开发。

Instruction level parallel processing is the key technology to improve the performance of current processors , while the control dependences caused by braches become bottlenecks of exploiting ILP .

以及两种成熟的拦截模式：杰弗瑞的输入节修改法和古老的导出函数入口跳转指令写入法。

Jeffrey 's import section alteration method and ancient jumper instructions method .

计算机程序设计中的一种跳转指令。

In computer programming , a jump instruction .

通过在一条无条件跳转指令之后立即插入无用数据，能够欺骗线性扫描方法。

The linear sweep method can be fooled by introducing garbage data immediately after an unconditional jump instruction .

它的一个指令周期由四个时钟周期组成，任何一条指令（包括跳转指令）都只需要一个指令周期就能完成。

Its instruction cycle is made up of four clock cycles . Every instruction can be executed in one instruction cycle .

在通常的应用程序中，间接跳转指令经常用来实现多目标分支语义，分支目标存放在跳转表中。

In regular binaries , indirect jumps are often used for multi-way branches , candidate targets are reserved in a jump table .

比如，使用进栈指令和跳转指令的一个组合，就可以混淆调用指令而实现对这个阶段的威胁。

This stage can be attacked by obfuscating the call instruction – say , by using a combination of the push and jump instructions .

只有在对跳转指令中占有比例较高的条件分支跳转进行一定优化后，才能有效减少由指令跳转产生的开销。

Only if the conditional branches jump instruction occupies a higher proportion in jump instruction is optimized , could it reduce the overhead efficiently generated by the jump instruction .

内核引导完成的主要功能是从磁盘上把内核装载至内存，读取系统硬件参数，设置全局描述符表、中断描述符表和页目录表，利用长跳转指令，从实模式切入保护模式。

Booting module gets information of the computer and configures the global descriptor table , interrupt descriptor table and page directory , after this , it use long jump instruction to go into protected mode .

依据这些信息，对攻击行为执行缓冲区边界检查，栈边界检查，返回地址保护和跳转指令检查，在缓冲区溢出攻击流程的关键节点拦截攻击，增强系统运行过程中的安全性。

Based on these information , make the attack code accepts the buffer boundary check , stack boundary check , return address check and jump instruction check , intercept attacks on the key nodes of buffer overflow attacks , enhance system dynamic security .

并与跳转相关指令的目标地址计算一起执行内存参考指令的地址计算。

Address calculations for memory referencing instructions are also performed here along with target address calculations for jump related instructions .

在FPGA内部不仅实现了CPU必需的算术逻辑器、寄存器堆、指令缓冲、跳转计数、指令集，而且针对FPGA内部的结构特点对设计进行了地址和数据的优化。

In FPGA , CPU IP Core have necessary arithmetic logic unit ( ALU ) , register stack , instruction buffer , Jump-counter , instruction-set , and optimize the performance of CPU based on the architecture of FPGA .

论文提出了一种跳转隐藏技术，它针对嵌入式应用中大量出现且占据大部分执行时间的短循环结构，通过隐藏跳转指令，增强流水线效率。

This paper puts forward a low-cost branch hiding technology for small loop , which takes up most of execution time of almost all applications .