指令缓存

Bochs的内部指令缓存为传统JIT编译进行了很好的权衡。

Bochs 's internal instruction cache provides a nice trade-off to traditional JIT compilation .

本文以符合ATSC标准的MPEG－2TS流解复用和系统信息解码为算法对象，研究在片上指令缓存有限的情况下设计嵌入式RISC核时，系统层解码的软／硬件协同设计。

Based on the design of demultiplexing and parsing procedure of MPEG-2 tranSPort stream , this paper presents the hardware / software co-design of the embedded RISC core , especially for the limited instruction cache size .

I-cache失效（处理器无法从指令缓存获取下一个指令）

I-cache miss ( Processor cannot get the next instruction from instruction cache )

在设计上突破传统思想的约束，采用可重构技术降低Cache的功耗。高速缓存设计模块中，实现了高速指令缓存和数据缓存高效协同运行，有效地提高了程序执行速度和数据存取效率。

In the policy design of instruction and data cache module , the instruction cache and data cache were applied to the system design and cooperated with each other effectively . This improves the program performance and the data access efficiency .

更有用的两个优化是更好的内联支持和利用指令缓存局部性的能力。

Two of the more useful optimizations are better inline support and the ability to exploit the instruction cache locality .

缓存页，使用页指令缓存整个页输出，而不管浏览器类型、各个参数或数据。

Caching pages , using either a page directive to have the entire page output cached , regardless of browser type , individual parameters , or data .

与将冷函数填入缓存相比，将热函数（也就是那些更常用的函数）放在一起可以更好地利用指令缓存。

Keeping hot functions together ( that is , those functions that are used more often ) results in better instruction cache use compared to polluting the cache with cold functions .

针对现代嵌入式处理器中指令高速缓存功耗显著的问题，提出一种基于Cache行间访问历史链接关系的指令高速缓存低功耗方法。

To reduce the power dissipation of instruction cache , which is more significant in modern embedded processor , a low power instruction cache accessing method , based on inter-line linking history , was proposed .

剩下所需做的就是使用本篇文章和上个月的那篇文章中所介绍的页面缓存指令来缓存整个页。

All that remains is to use the page caching directives you saw in this article and last month 's to cache full pages .

当一个缓存行中包含有有效的缓存数据或指令时这个缓存行就是有效的，反之是无效的。

A cache line is said to be valid when it contains cached data or instructions , and invalid when it does not .

为了解决这个问题，近年来开发的一些嵌入式处理器芯片包含了指令和数据缓存锁定功能以防止其中的数据被交换出去。

To solve this problem embedded processors developed these days has the ability to lock instruction and data cache to prevent the contents in them from being swapped out .

指令must-revalidate强制所有缓存都验证响应。

The directive must-revalidate forces all caches to validate responses .

这些指令通常覆盖默认缓存算法。

These directives typically override the default caching algorithms .

这些指令指定用于阻止缓存对请求或响应造成不利干扰的行为。

The directives specify behaviors intended to prevent caches from adversely interfering with the request or response .