分频

在一片CPLD中集成了低位地址锁存、地址译码、数据总线、分频电路、比较、记数以及逻辑电路等。

It integrated flip-latch , coding unit , data bus , frequency division unit , logical compare unit , counter and logic circuit into a single CPLD chip , and dramatically decreased PCB 's area and increased system reliability .

通过GPS接收机解调出PPS秒脉冲信号，并把此信号与系统晶振分频的信号同步，产生了各种频率的同步时间信号，送给其它的测试设备，就完成了整个系统的同步。

PPS pulse signal is demodulated by GPS receiver , and synchronized with the crystal frequency division signal of system . A variety of frequency synchronization time signal is produced and sent to the other test devices and the synchronization of the system is completed .

n为所要求的非整数分频值。

N is the desired noninteger frequency divider .

应用于GPS接收机频率综合器分频器的设计

The Design of Divider for Frequency Synthesizer Applied in GPS Receiver

基于FPGA的半整数及整数分频器的参数化设计

Parameterized Design of Half-Integer and Integer Frequency Dividers Based on FPGA

基于FPGA技术的16位数字分频器的设计

Design of sixteen bits digital frequency divider based on FPGA

基于FPGA的小数分频频率合成器设计

Design of fractional frequency dividing frequency synthesizer based on FPGA

一种改善AR谱估计性能的分频段方法

A Method for Improving AR Spectrum Estimation by Dividing Frequency Band

应用于OFDMUWB系统的高速分频器研究与设计

Research and Design of High-speed Frequency Dividers for OFDM UWB System

0.6μMCMOS静态分频器电路设计

Static Frequency Divider Circuit Design Using 0.6 μ m Standard CMOS Process

通过合理设计前端双模预分频电路、可编程P计数器和S计数器可实现任意分频比。

The random divide ratio can be get with the help of designing the dual-modulus prescaler , programmable P counter and S counter exactly .

一种低功耗CMOS分频电路设计技术

A low power dissipation CMOS divider design technique

CMOS高性能奇数分频器的设计

The Design of High Performance CMOS Odd Divider

GaAs高温栅全离子注入平面工艺及GaAs数字二分频器

GaAs full Ion Implantation and Refractory Gate Planar Process and GaAs Digital Divider

一种由三分频PWM波到方波转换的方法

A Method for Pulse Dropping in the Change from a PWM Waveform to a Square Wave

基于CPLD的任意整数半整数分频器设计

Arbitrary Integral or Half-integral Frequency Division Designed with CPLD

介绍了典型N数字小数分频器的工作过程，在此基础上分析了由级联累加器实现的积分功能。

The working process of typical N Digital fractional frequency divider is introduced and the integration function performed by cascaded accumulators is analyzed .

可以对增量式编码器输出的AB相信号进行整数分频。

Incremental encoder can output an integer number for AB believe frequency .

GaAs高速动态分频器在片测试研究

On-Wafer Testing of High-Speed GaAs Dynamic Frequency Divider

基于CPLD的数字移相分频钟

A Digital Phase-Shifting Frequency-Dividing Clock Designed with CPLD

在CPLD中实现音频信号分频的计算方法，给出了设计原理图；

Audio signal frequency is implemented in CPLD , give the schematic of the designing .

发射极条宽为3微米时，fγ>3GHz。该工艺已应用于超高速双极ECL分频器中。

This technology has been applied to very high speed bipolar ECL frequency dividers .

半整数分频器的VHDL设计

The design of half integer frequency divider with VHDL

使用搜索算法，我们可以确定可能的N分频值并使用相应的压控振荡器频率来确定Q和P值。

Using a search algorithm , we can determine the possible N divide values and use the corresponding VCO frequencies to determined Q and P values .

阐述了在不提高外部振荡频率的前提下，保证各唱名频率精确度的方法，给出了用ABLE语言编写的实现小数分频器和控制、译码电路程序。

With on increase of the exterior oscillation frequency , the precision of the note frequency is secured . The control and decode sequence is composed with ABLE language .

根据项目指标要求，以上述两种分频器为基础，重点构建了由7/8预分频和P、S计数器组成的多模分频器结构。

According to requirment of project target , a multi-modulus divider constituted with a 7 / 8 prescaler and P , S counters , is designed with the two proposed divider .

WSN射频芯片中6GHzRFCMOS低功耗双模前置分频器的设计

Design of 6 GHz RF CMOS Low-Power Dual-Modulus Prescaler in WSN RF Chips

在这个CML分频器基础上，设计了一个可编程分频器。

Based on the CML divider , a programmable divider was implemented .

利用该系统在片检测了GaAs高速数字集成电路动态分频器内部的高速电信号。

The high-speed electric signals at internal points in the high-speed GaAs digital integrated circuit-dynamic frequency divider were measured .

提出了一种分数阶Fourier域的图像分频率压缩感知算法。

Discusses the feasibility of the program . 2 . A image sub-frequency compressed sensing algorithm based on fractional Fourier transform is proposed .