部分积

部分积产生器主要采用BoothⅡ型算法，大大减少了乘法累加操作中产生的部分积数目，从而提高整个乘法累加器的运算速度；

The partial product producer mainly uses the Booth II algorithm , reduced the partial product number greatly which in the multiplication accumulation operation produces , thus enhances the entire multiplication accumulator the operating speed ;

随后提出了自己的乘法器设计架构，设计了一个30管的编码电路和传输门结构的部分积产生电路以及一种界于Wallace树和重复阵列之间的折中压缩结构。

After that , the multiplier architecture of mine was proposed . A 30-transistors encoder and the circuit of the generation of partial product with translation gate , and a compression architecture between Wallace tree and iterative array was designed .

用简化部分积的扩展符号位所在全加器的连接的方法提出了一种适于VLSI实现的并行乘法器结构。

A parallel multiplier configuration especially suitable for VLSI realization is presented .

乘法器采用改进的Booth算法，简化了部分积符号扩展，使用Wallace树结构和4-2压缩器对部分积归约。

This multiplier used modified Booth Algorithm , Wallace tree and 4 - 2 compressor .

该乘法器采用了改进的Booth算法减少部分积的个数；

In the multiplier unit , we use modified Booth algorithm to reduce the number of partial products .

在三时钟PE的微结构中，改进了一种双域Wallace混合树型结构对部分积进行压缩。

In the micro-architecture of triple-clock PE , a hybrid dual-field Wallace tree is modified to compress the partial product .

为减少硬件消耗，乘法器使用的部分积由修改的Booth算法产生。

To save the delay time and hardware resources , multiplier uses the partial products generated by modified Booth algorithm .

进位传输加法器是将所有的部分积相加产生2n位的结果，是为了生成最终结果。

Carries transmits the accumulator is adds together all partial products and produces the 2n position result for produce the final outcome .

本文针对典型32位乘法，对Booth算法产生的部分积重新合理分组，采用CSA和4-2压缩器的混合电路结构，对传统的Wallace树型乘法器进行改进，提出一种高速的树型乘法器结构。

This paper proposes a novel architecture of multiplier for the typical 32 × 32 multiplication . It bases on the modified traditional Wallace-tree multiplier , and adopts both CSA and 4-2 compressor .

理论上Wallace树结构加法器是乘法器中完成部分积求和的最快的多操作数加法器，但其互连复杂难于实现。

Wallace trees are the theoretically fastest multi operand adders , which can be used for obtaining the sum of partial products . However , their complex interconnections do not permit practical implementation .

对于BOOTH编码和部分积产生，提出了直接建立被乘数与部分积的多路选择映射关系的BOOTH编码和部分积联合产生方法；

For the partial products generation , the novel method of Booth encoding combined with partial products generating is put up , which can directly map the multiplicand and multiplicator to partition products without generating the BOOTH encoding results .

首先设计出4-2和3-2压缩器，然后由其构成wallace树结构的压缩器，在部分积整个压缩过程中，采用三级流水线，大大提高了浮点运算中尾数处理的速度。

Firstly , The compressor of 4-2 and 3-2 is designed , which are used to structure wallace tree compressor . In the process of compression three class pipelines is introduced for the purpose of greatly improving speed of mantissa processing in the floating operation .

该体系结构首先将DCT／IDCT中的常系数乘加运算分散为部分积加法运算，然后通过共享公共子表达式减少加法数量，最后用优化的Wallace树汇总部分积以计算最终结果。

This DCT / IDCT architecture distributes the multiply / accumulate with fixed coefficients into additions for partial products at first , then decreases the number of additions by sharing subexpression , and accumulates all partial products to get the transform result based on optimized Wallace trees at last .

本文提出了一种新的部分积消减树生成算法。

A new Algorithm of Partial Products Reduction is given .

使用同一套电路处理无符号数乘法和有符号数乘法，并且简化了部分积的符号扩展。

The multiplier uses the same circuit to deal with operand with or without sign .

同时，通过子模块合并技术将参与部分积求和运算的子模块数控制在分块数的两倍。

And then control the number to be no more then twice of the significant digits portion .

在设计中重点研究了部分积生成和压缩电路的结构，最后得到了理想的设计结果。

Part product producing and compressing are researched in the design . It gets a good result .

部分积的产生中采用了有限符号扩展技术，减小了部分积的长度。

In partial product generation , we adopted limited sign extension technique which reduces the length of partial product .

设计完成的乘法器只产生9个部分积，有效降低了部分积压缩阵列的规模与延时。

The designed multiplier has only 9 partial products , which effectively reduces the size and delay of compression array .

在确保速度的前提下，文章通过三种独立的方法减少部分积压缩器中的加法器数目，从而对面积进行了优化。

In condition of high speed , the paper also gives three methods to reduce the number of adders in compressor in order to optimize the area .

32位乘法器采用改进的基4布斯算法减少部分积的个数；并通过数学计算预处理符号扩展，使得部分积符号扩展电路简单规整。

32-bit multiplier adopts modified radix-4 booth coding to reduce the number of part products , simplifys the sign extending circuit of part product by the mathematical preprocessing .

通常来讲，产生部分积的数目越少的算法，其电路越复杂，因此需要综合两点考虑来选择合适的算法。

Generally speaking , the fewer partial product , the more complex and slower the partial product circuit is , so both need considering to select the best algorithm .

通过对部分积的符号扩展、（k：2）压缩器、连线方式和最终加法器分割算法的优化设计，可以在18.81ns内完成一次乘法运算。

An 18.81-ns multiplication time is achieved at 50 MHz , by optimizing modified signed extension algorithm , ( k : 2 ) compressors , connection algorithm and partition method of final adder .

本文描述了一种32×32位快速并行结构乘法器，介绍了基于修正布斯编码算法的部分积产生电路，并对部分积的符号扩展进行了简化。

This paper describes the design of a kind of 32 × 32bit fast parallel multiplier , introduces partial product generation circuit based on modified Booth algorithm , Wallace tree and 4 ∶ 2 compressor .

针对Radix-4Booth编码乘法器，提出了一种完全消除部分积生成时加法运算的方法，有效地减小了关键路径延迟和芯片资源消耗。

Aiming at the multiplier based on Radix-4 Booth encoding , a method entirely eliminating additive operation on partial product generating is advanced , which effectively decreases crucial path delay and chip area consumption . 4 .

对于传统的乘加运算，充分利用分布式算法，构造两个查找表，一个表用来更新滤波系数，另一个用来产生部分积。

Compared to the traditional operation of addition and multiplication , constructing two lookup-table to implement the multiplication operation so as to take full advantage of a distributed algorithm . One table is used to update the filter coefficients , and the other is used to generate partial products .

全脑室积血组死亡率高于部分脑室积血组（Logistic回归分析P<0.05，χ2检验P>0.05）；

The mortality in all ventricles hemorrhage of the brain was higher than the mortality in partial ventricles hemorrhage of the brain by Logistic regression analysis ( P < 0.01 ) .

对拟完全可积共振或部分可积系统，Lyapunov函数取为系统的独立对合首次积分的最优线性组合。

For quasi-integrable and resonant Hamilton systems and quasi-partially-integrable Hamiltonian systems , the optima linear combination of the independent first integrals in involution is taken as the Lyapunov function .

部分图笛卡儿积图的邻点可区别VE-全染色

Adjacent vertex-distinguishing VE-total coloring of Cartesian product graph of some graphs

砂质碎屑流和底流改造&部分传统浊积岩成因新解

Sandy debris flow and bottom current reworking : a new interpretation of the formation of a part of traditional turbidite