乘法器

C可测乘法器的设计与测试

Design and Test of a C - Testable Multiplier

通用乘法器IP核可测性设计研究

Research on the design for the testability of the general multiplier

高效结构的多输入浮点乘法器在FPGA上的实现

Implementation of an High Performance Structured Multiple-input Floating-point Multiplier on FPGA

基于可编程逻辑器件的高速乘法器IP设计

IP design of fast multiplier based on PLD

基于FPGA的高速流水线浮点乘法器设计

The Design of High Speed Pipeline Floating Point Multiplier Based on FPGA

基于FPGA的乘法器实现结构分析与仿真

The Analysis and Simulating for FPGA-Based Multiplier Implementation Structures

单周期控制无乘法器三相电压型PWM整流器

Three-Phase Voltage Source Type PWM Rectifier by One-Cycle Control Without Multipliers

模拟乘法器模块分析的CAI软件设计及编程技术

The CAI Software Design and Its Programming Technique for Analog Multiplier Analysis

基于Booth算法的32×32乘法器IP核设计

A 32 × 32 Multiplier IP Using Booth Algorithm

本文提出了一种CMOS四象限模拟乘法器。

A CMOS four-quadrant analog multiplier is proposed in the paper , which .

本文然后讨论了脉动矩阵乘法器的设计，最后讨论了3D几何图形加速引擎的结构。

Then a systolic array Multiplier is discussed . At last , structure of the 3D accelerating graphics engine is analyzed .

一种低电源电压的CMOS四象限模拟乘法器

A Low Power-Supplies ' CMOS Four-Quadrant Analog Multiplier

高频电流模四象限CMOS模拟乘法器

CMOS four-quadrant analog multiplier with high frequency capacity

本文利用基于模代数的三值通用逻辑门&Uk，设计了一位三值全加法器和全乘法器电路。

In this paper , one-bit ternary full-adder and full-multiplier are designed by using ternary universal-logic-gate-UkS based upon modular algebra .

该乘法器可以应用于RS（255223）码编/译码器。

The circuit for computing multiplications can be used in RS ( 255,223 ) codecs .

一种高效的可伸缩分组并行有限域乘法器及VLSI实现

An Efficient Digit - Serial Finite Field Multiplier and Its VLSI Implementation

一种快速有限域乘法器结构及其VLSI实现

A Fast Finite Field Multiplier Architecture and Its VLSI Implementation

基于ADSL系统RS纠错码的乘法器及倒数器的设计

Design of Multiplier and Inverses of Multiplier for Reed-Solomon coding in ADSL System

几种模拟乘法器在ECT硬件系统中的应用比较

Compare several analog multipliers applied to ECT hardware system

浮点乘法器中IEEE舍入的实现

Implementation of IEEE Rounding in Floating Point Multiplier

并给出了它们各自三阶互调失真的表达式，最后又对AGC放大器和乘法器进行了分析和比较。

It also analyzes and compare the theory of AGC Amplifier and Multiplier .

基于FPGA乘法器架构的RNS与有符号二进制量转换

RNS to Binary Signed Conversion Based Multiplier on FPGA Architecture

电阻耦合型神经MOS晶体管及其差分四象限模拟乘法器

The Resistance Coupling Neuron MOS Transistor and It 's Difference Four-quadrant Analogue Multiplier

应用EDA技术实现并列乘法器

Realization of Parataxis Multiplicative Implement by Application of EDA

在乘法器单元中采用BOOTH算法和先进进位加法器相结合的单元设计；

The multiplier unit adopts the BOOTH algorithm and carry lookahead adder ;

多位乘法器的多阶Booth算法的实现一种快速大数乘法器的设计方法&大数乘法的高速实现

Multi-radix Booth Algorithm of Multi-bit Multiplier One Large Multiplication 's Fast Implementation

改进型booth华莱士树的低功耗、高速并行乘法器的设计

Low Power and High-Speed Parallel Multiplier Design Using Modified Booth Wallace Tree

基于改进的BOOTH编码的高速32×32位并行乘法器设计

High-speed Parallel 32 × 32-b Multiplier Design Using Booth Encoders

在此基础上，提出了基于分布式算法的无乘法器全流水线DCT硬件结构。

Then , a no-multiplier , DA based , pipelined DCT hardware architecture is presented .

常系数FIR中的CSD串并乘法器设计

Design CSD Serial-Parallel Multiplier for Constant Coefficients FIR Filter