数据和时钟线都是集电极开路的。
The Data and Clock lines are both open collector .
在TTL与非门电路中，输出级改用集电极开路的一种反相器。
In TTL NAND circuit , a phase inverter with its output circuit changed to an open collector .
总线空闲时，两条线都是高电平（集电极开路）。
The bus is " idle " when both lines are high ( open-collector ) .
集电极开路