数据通路

重点讨论了ALU的资源部件、数据通路、指令及在设计中的平衡规则。

It is given that detailed design of the ALU unit , includes the execution unit , datapath , instruction and the trade-off in the design .

提出了一种基于演化程序的数据通路综合算法，该算法是将演化程序与已知的启发式算法相结合来对较大的设计空间进行智能化搜索；

The approach to datapath synthesis based on an evolution program combines an evolution program with a known heuristic algorithm to search the larger design space in an intelligent manner .

设计RISC51IPCore数据通路，重点是算术逻辑运算单元的实现。

Design the data path of the RISC 51 IP CORE . emphasis on the Arithmetic Logical Unit ; 3 .

DSP数据通路基于累加器测试的结构可测性设计

Structural design-for-testability of accumulation-based testing for DSP data path

介绍了高性能定点可重构DSP处理器的数据通路设计。

In this paper , the data path of a high performance reconfigurable DSP processor is introduced .

详细介绍了C单元和异步数据通路的设计与实现，提出了一种异步实现结构的异步加法单元、异步比较单元和异步选择单元电路。

The design and implementation of C element and asynchronous data-path are introduced . The circuits of asynchronous adder unit , asynchronous comparator unit , and asynchronous selector unit are proposed .

功耗限制下RTL数据通路非扫描BIST方法的延时分析

Studies on Delay Overheads of Power-constrained Non-scan BIST Methods for RTL Data Paths

本文主要研究J2ME安全数据通路的设计和实现。

The main work of this paper is the design and realization of the J2ME secure data channel .

RPR中数据通路的分析

Analysis of data path in RPR

NiosⅡ的自定制指令是与CPU的数据通路中的ALU相连的用户逻辑块。

Nios ⅱ custom instructions is an user logic block which is connected with the ALU from the CPU data path .

针对RTL数据通路，本文提出一种测试综合与调度方法。

In addition , for RTL data path , this thesis proposes a test synthesis and scheduling approach .

该异步乘法器采用8位Booth译码乘法算法，在数据通路上采用3级循环流水结构，并采用4-2压缩模块以提高乘法速度。

A 3-stage iteration pipeline structure and 4-2 compressor rows are adopted in the data path module , using 8-bit Booth decode algorithm .

FC接口逻辑的数据通路宽度为16比特，支持1.0625Gbps和2.125Gbps的光纤通道应用，可用于点对点拓扑和交换机拓扑。

The data path width of Fibre Channel interface logic is 16-bit.1.0625 Gbps or 2.125 Gbps Fibre Channel applications , point-to-point topology and Fabric topology are supported .

所设计的RFID数字基带包括发送和接收两条数据通路，可实现PIE码的编码及发送，以及Miller码的解码和接收。

The RFID baseband includes Tx and Rx two data path which can realize the encoding and sending of PIE code , decoding and receiving Miller code as well .

通过采用调试接口电路的流水线映像寄存器组和特殊数据通路，可以避免在CPU关键路径上插入扫描链实现“非侵入性”的调试功能。

By using pipeline shadow registers and special data path in debug interface circuit , scan chain is no longer needed to insert in the critical path of CPU to facilitate non-intrusive debug capability .

本论文从DiffServ模型总体结构的基础上，研究了数据通路和控制通路的关键实现技术和实现结构。

The thesis , on the basis of the DiffServ model architecture , study the key realization technology of the data path and control path .

提出了一种在利用约束逻辑编程生成RTL数据通路模拟矢量的方法中处理宽数据的新方法。

This paper proposes a new approach for dealing with wide data in automatic simulating stimuli generation using constraint logic programming ( CLP ) .

最后测试了语音处理模块的压缩回放质量以及信号处理模块的Codec功能和数据通路。

Finally , the compression playback quality in voice processing module , functions of the Codec and data path in signal processing module in signal processing module are being tested .

在初始数据通路和流水线节拍设计的基础上，根据对马氏距离计算特点的深入理解分析，从SRAM模块和乘法器资源两个方面进一步优化了设计。

Base on the initial data path and pipeline design , we make some optimization for SRAM module and multiplication resource by the deep analysis of Mahalanobis distance calculation .

本文在硬件平台上对底层的数据通路进行配置调试后，进行基于OFDM技术的收发联调，成功实现了通信。

After configuration and debugging has operated on the data path on the bottom hardware , this paper finishes the joint debugging of sending and receiving based on technology of OFDM , the requirement of communication has realized successfully .

本文还完成了HDLCIP核数据通路和控制通路各个层次模块的设计规划，使用硬件描述语言Veriloghdl实现了IP各模块的设计；

Every level module of the data path and controller of HDLC IP core was designed and every unit 's design of HDLC IP core was programmed with the Hardware Description Language ( Verilog HDL ) .

第三章详细阐述了GPIB控制器的十种接口功能及其状态机实现，完全遵循IEEE-488协议规范。第四章对数据通路进行了较为细致的说明。

Chapter three introduces the GPIB controller interface function , especially the designing of state machine according to IEEE-488.Chapter four introduces the designing of data channel .

在控制平面主要介绍了建立维护数据通路时所需的相应控制平面的基本过程；用户平面通过使用NAT技术，可以使SGSN和外部IP网进行用户面数据的交互。

In control plane , this paper introduces the process that is used to create and maintain date path . In user plane , SGSN could communicate with other IP network by NAT technology .

根据数据通路所需要的控制信号，设计能使数据通路有效工作的控制通路；采用VHDL实现控制通路和中断控制器。

According to the control signal needed by the data access , control access that can make the data access well-functioned is designed ; VHDL is used to realize control access and break controller . 4 .

针对寄存器传输级（RTL）数据通路，文献[1]提出了两种功耗限制下非扫描内建自测试（BIST）方法。

In particular , the increased delay may cause delay faults . paper [ 1 ] proposed two power-constrained non-scan BIST methods for register transfer level ( RTL ) data paths .

该系统接受DDL语言，并通过翻译、数据通路综合、控制部分综合及硬件约束等几个变换过程，生成由器件库中存储的、与实现技术相关的硬件模块组成的结构描述。

Accepting DDL description , the system can generate structure description consisting of technology-dependent hardware modules in module library , by translation , data path synthesis , control part synthesis and hardware binding .

介绍了模型机的结构与数据通路的基本组成，分析了各部分的功能及各类数据在模型机中的流动过程，给出了用VB制作演示程序的方法。

The structure of normatron and the components of the data channels are introduced , along with analysis of the functions of the components and the flowing process of various data and the method of compiling demonstration program by means of VB is given .

该设计流程充分利用了现有的同步集成电路EDA工具，将异步控制通路中的关键单元全定制为宏单元，同时异步数据通路的设计仍采用同步集成电路的设计方法。

The design methodology uses many existing synchronous EDA tools . The critical circuit components of the control path of asynchronous circuits are designed as macro cell . The data path of the asynchronous circuits is designed with traditional synchronous design methodology .

围绕基于微处理器核的AAC解码器结构设计展开讨论，对IP定制、数据通路及存储设计进行了研究，并成功开发了一个基于微处理器核的MPEG-4AAC解码系统芯片。

This paper studies the design of IP configuration , data paths and memory design , focusing on architecture design of AAC decoder SoC based on microprocessor core . Finally , an MPEG-4 AAC decoder SoC chip based on embedded microprocessor is developed successfully .

论文深入研究了微处理器的指令系统，设计了微处理器数据通路，采用硬件描述语言完成了ALU单元、取指单元等电路模块的设计与实现；

The thesis carefully researches on repertoire of microprocessor , designs the data path , and completes the design and realization of ALU unit , instruction fetch and so on by Hardware Description Language ;