寄存器文件

之后本文在MarchC-算法的基础上，结合shadowread和shadowwrite技术，首次提出了针对20端口寄存器文件的BIST算法。

Then , the thesis , based on March C - algorithm , shadow read and shadow write technologies , put forwards BIST arithmetic for the 20-port register file .

最后，介绍了银河飞腾D4高性能DSP中的全定制设计模块桶形移位器与寄存器文件的视图产生过程。

Finally , the view-generating process of a full-customized barrel shifter module and register file module in a high performance DSP is presented .

X处理器中高速寄存器文件全定制设计与实现

Full Custom Design and Implementation of High-Speed Register File in X Processor

基于EPIC动态同时多线程寄存器文件管理机制的研究

Research on Register File Management for the DSMT Architecture Based on EPIC

软件仿真结果表明，对DSP中不同的应用程序平均可以减少94%的寄存器文件写次数。

The results of simulation show that the average number of write operation on RF is reduced by 94 % for various application programs .

对这种局部变量就没有必要将流水输出结果写回寄存器文件，以减少对寄存器文件（RF）的读写操作次数，从而降低对寄存器文件端口的读写要求。

In this case , it is not necessary to write their values back into register file ( RF ) . Thus the requirement of read / write operation on RF is reduced .

寄存器文件被广泛地应用于最新的DSP和媒体处理器的设计，为了能够减小处理器所开销的芯片面积、功耗以及体系结构的复杂度，必须合理设计寄存器文件结构。

RF ( register file ) has been widely used in latest DSP and media processor designs . In order to reduce the chip area and power consumption and architecture complexity , it is necessary to design a reasonable RF configuration .

在以上关键技术研究的基础上，本文还研究了VIM体系结构下向量协处理器的实现技术，包括标量指令集的扩展方式，多端口寄存器文件的实现，向量执行单元的流水线设计等。

This thesis also focused on implementation technology of vector microprocessor based on VIM architecture , including KD-VIM-1 ISA defination , multiported register file and vector execution pipeline etc.

新一代面向密集计算的高性能处理器普遍采用分布式寄存器文件来支撑ALU阵列，并通过VLIW开发指令级并行。

Newly-emerging high performance processors for intensive computing generally use distributed register files to support ALU array and to explore instruction level parallelism ( ILP ) by VLIW .

V-PIM中低功耗分体多端口向量寄存器文件设计

A Low Power Banked Multi-Ported Vector Register File Design for V-PIM

TTA中，软件所见为功能单元（FU）之间的数据传输，故硬件设计可以支持寄存器文件分割以及定制更多更复杂的FU，同时解决了指令集生成、可重定向编译等问题。

In TTA , software specifies data transports among function units ( FUs ), so application specific hardware can support more sophisticated FUs , and the problems about instruction generation and retargetable compiling can be solved at the same time .

PPE用载入和存储指令访问主存储器（有效地址空间），可以在主存储器与内容可以缓存的私有寄存器文件之间移动数据。

The PPE accesses main storage ( the effective-address space ) with load and store instructions that move data between main storage and a private register file , the contents of which may be cached .

实验表明基于存储器着色的SRF分配框架能够在不引入溢出的前提下，有效地开发复用和并行。（3）提出了基于最佳有向路径寻找的流寄存器文件分配算法。

The experiments show that the memory coloring based framework could efficiently exploit reuse and parallelism , without introducing spills . ( 3 ) Proposes an optimal directed path searching based stream register file allocation algorithm .

在JTAG接口协议的基础上，增加指令和扫描链，同时通过测试访问端（TAP）控制把串行输入转换成并行输出，并行访问数字信号处理器的寄存器文件和片上存储器单元，实现嵌入式模拟器。

Based on the jointed test action group ( JTAG ) protocol , instructions and scan chain were introduced . With test access port ( TAP ) module exchanging serial input with parallel output , register files and random access memory on chip were read or written in parallel .

文章介绍了采用0.13！m、1.2V工艺实现的600MHz、144×65位、20端口（8写12读）通用寄存器文件。

A 600 MHz , 144 × 65-bit , 20-port ( eight-write-port , twelve-read-port ), general register file has been designed for 1.2 V 0.13 ?

大规模、多端口高速寄存器文件全定制设计与实现

Full Custom Design and Realization of Large-scale Multi-port High Speed Register File

一种新的减少媒体处理器中寄存器文件复杂度的方法

A new method of reducing the complexity of register file in media processors

寄存器文件的研究与全定制实现

The Study and Full Custom Implementation of Register File

多端口高速通用寄存器文件设计优化

Design and Optimization of High-speed Multiported General Register File

高速5端口寄存器文件的设计与实现

Design and Implement of a High-Speed 5-Port Register File

寄存器文件的优化设计对提高微处理器的性能至关重要。

An optimized design of register file is critical to the performance of microprocessor .

这些结果然后在有序退回时，存放在一个独立的结构寄存器文件中。

These results are then committed to a separate architectural register file during in-order retirement .

数字信号处理器中10端口高速寄存器文件设计

A 10-Port High-Speed Register File in DSP

软硬件协同减少媒体处理器中寄存器文件写次数的方法

Software and hardware co-design for reducing the number of write on register file in media processors

为了隐藏访存延迟，网络处理器往往采用较大的寄存器文件，增加寄存器的数量。

To hide memory latency , NPs employ large register file for large number of registers .

然后，面对分体寄存器文件可能产生端口冲突的新问题，提出了改进的基于图着色的寄存器分配法。

Firstly , this paper proposes a modified register allocation via graph coloring to alleviate port conflicts .

此支持40－物理寄存器文件，此文件含有能混序完成的临时回写结果。

This supports a40 - entry physical register file that holds temporary write-back results that can complete out of order .

缓解集中式向量寄存器文件可能造成的瓶颈，用比较灵活的方式来分解访问冲突；

Overcome the bottleneck of the centralized vector register files , and resolve the accessing conflict in a relatively flexible way ;

本文设计了一款支持多线程的高性能通用寄存器文件，它有3个读端口和2个写端口，支持4线程并行。

There are 3 read ports and 2 write ports in the register file which support 4 threads running in parallel .

因此，设计具有高能性、低功耗，多端口的寄存器文件是一项非常有意义的工作。

Therefore , design a register file that owns features of high-performance , low-power and multi-ports is exactly a meaningful work .