动态功耗

动态功耗管理（dynamicpowermanagement，DPM）是一种较为有效的低功耗设计技术。

Dynamic power management ( DPM ) is an effective technique for low power design .

CMOS电路的最大动态功耗计算和测试生成

Calculation and Test Generation of the Maximum Dynamic Power Consumption lor CMOS Circuits

CMOS电路功耗主要由动态功耗决定。

Power dissipation in CMOS circuit is decided mainly by the dynamic power dissipation .

VLSI的动态功耗测试生成

Test Generation of the Dynamic Power Consumption for VLSI

系统级动态功耗管理（dynamicpowermanagement，DPM）策略根据系统状态和负载，动态地调整系统配置，从而能够有效降低系统功耗。

System-level dynamic power management ( DPM ) techniques observe the status and workload of the system , and dynamically reconfigure the system to reduce power consumption .

CMOS电路的动态功耗大约占全部功耗的70%～90%。

The dynamic power of CMOS circuit is responsible for 70 % ~ 90 % of the total power .

这种技术在不影响性能的前提下，可以根据IP核的应用状况自动开关时钟，不但可以降低动态功耗，还可以结合门控电源技术降低漏电功耗。

ACG can automatically turn on or turn off the IP clock to not only reduce dynamic power but also reduce leakage power with the power gating technique .

而且根据不同的编码参数，可适当地屏蔽某些RAM，有效降低系统的动态功耗。

And according to different encoding parameters , the dynamic power consumption can be effectively reduced by properly shielding some RAM .

基于数据缓冲区的PMP硬盘动态功耗管理策略

Data Buffer Based DPM Policy for Hard Disk in PMP

实验结果表明相比较常规SRAM，LVBSSRAM可以节约30%的动态功耗。

Experiment result shows LVBS SRAM saves 30 % dynamic power compare to conventional SRAM ' s.

对一款真实SoC中浮点IP核的改造实验表明，在不降低性能的前提下，可以平均降低62.2%的动态功耗，同时理论上平均降低70.9%的漏电功耗。

The experimental results on some IP cores in a real SoC show an average of 62.2 % dynamic power reduction and 70.9 % leakage power reduction without performance degradation .

本文所建立的SoC长互连动态功耗分析平台和低功耗设计方法，为新型SoC低功耗设计提供了重要的技术基础。

The platform for power dissipation analysis of SoC long interconnects and low-power design methods this paper proposed provide an significant technology foundation for novel SoC low-power design .

如何提高预测的准确度是当前基于预测动态功耗管理（DPM）研究的主要问题。

How to improve predictive accuracy is the main problem needed to be solved in DPM policy based prediction .

通过分析CMOS电路功耗产生原因，介绍了动态功耗管理、门控时钟和操作数隔离等低功耗设计方法，给出了该AES密码算法详细的低功耗实现方案。

By analyzing the source of CMOS circuit 's power consumption , a detailed solution which considered several low-power techniques , such as dynamic power management , clock gating and operand isolation , was provided .

采用结构优化方法优化SPM结构，实验数据表明优化后的SPM动态功耗降低了25%，而面积和延时仅仅增大了8%和2%（系统要求功耗优先）。

The experimental simulation results indicate that SPM reduces 25 % dynamic power , but merely increases 8 % area and 2 % delay ( system requires power preference ) .

最后把各个功能模块组合成在一起，设计出了低功耗的Viterbi译码器，仿真结果表明比起没有采用低功耗技术的译码器，在译码器纠错性能和译码速度不变的情况下，动态功耗降低了33%。

Our experimental result shows the proposed design reduces the dynamic power dissipation of a Viterbi decoder by about 33 percent compared with the one without considering the low-power design .

动态功耗是由于CCD驱动时钟对时钟电极的串联等效电容或极间电容进行充放电，充放电电流流过多晶硅电极电阻或串联等效电阻引起功率耗散。

Dynamic power dissipation , however , is the energy dissipation caused by the charged or discharged current flowing through the resistance of polysilicon clock line and the series equivalent resistance of the clock electrode when the clock pulse is applied to the device .

分别给出了二者的估算方法，其中动态功耗的估算方法有集总模型估算法、分布式模型估算法及PSpice仿真估算法三种。

The methods to estimate these two power dissipations are proposed in this paper . As for estimating the dynamic power dissipation , lumped model , distributed model and PSpice simulating are presented in detail .

通过对Fibonacci型电荷泵上升时间的估算，对减小上升时间和动态功耗进行折中考虑，本文提出优化开关频率的方法。

By estimation of the rise time of the Fibonacci like charge pump , an optimal switching frequency is suggested to make a compromise between the rise time and the dynamic power dissipation .

CMOS集成电路功耗的物理来源主要有两种：由于CMOS管工作状态变化而引起的动态功耗和由于漏电流而产生的静态功耗。

It has two main source of power dissipation for CMOS integrated circuits : the dynamic power dissipation , which is caused by the change of CMOS transistor working state , and the static power dissipation , which is caused by the leaking current .

该方法通过设立缓存地址映射表，记录TLB表项在缓存中的地址映射，可有效减少缓存中TLB表项的访问次数，降低动态功耗。

This method set up cache address mapping table , which recorded the location of TLB entry in Cache , to decrease TLB accesses with less dynamic power consumption . 2 .

其中，设计了一个新颖的多数投票器电路结构，具有速度快、动态功耗低和零静态功耗的优点，对降低BI空间编码器引入的能耗和延时开销具有重要作用。

This technique has a highlight that the BI spatial encoder is based on a novel majority voter circuit with desirable merits such as high-speed , low-power operation and near-zero static power , thereby , resulting in significantly reduced energy and delay overhead of spatial encoder .

本文是针对卷积码约束度为9的Viterbi译码器的低功耗设计研究。在CMOS技术中，器件的功耗主要来源于信号变化产生的动态功耗。

In this thesis , we investigated a low-power design of Viterbi decoders that constraint length equal 9 . In CMOS technology the major source of power dissipation is attributed to dynamic power dissipation , which is due to the switching of signal values .

SRAM的功耗可分为静态功耗和动态功耗，工作在亚阈值区域的SRAM存储单元功耗很低但其稳定性也更容易受到工艺、电源电压及温度（PVT）的影响。

The power consumption of SRAM can be divided into static and dynamic power consumption ; SRAM memory cells which works in the sub-threshold area have a very low power consumption but their stability is also more susceptible to process , supply voltage and temperature ( FVT ) .

许多研究只考虑了检查点的时间开销，本文从检查点实现过程、动态功耗组成及DVS原理等方面研究认为在某些情况下检查点的功耗开销必须要考虑。

Much literature only dealed with time cost of checkpointing . After research on the principle of checkpointing , the makeup of dynamic power and the principle of DVS , a conclusion is got that sometimes the power consumption of checkpointing must be considered .

一种数字信号处理器的动态功耗管理方案

A Dynamic Power Management Scheme for the Digital Signal Processor

基于随机决策模型的动态功耗管理策略研究

Study on Policy of Dynamic Power Management Based on Stochastic Decision Models

SCANGIN：一种降低扫描测试中动态功耗的方法

SCANGIN : An Approach for Reducing Dynamic Power Dissipation in Scan Test

基于软件测量与控制的动态功耗管理预测策略

Predictive dynamic power management policy based on measure and control by software

门控时钟技术一直以来是降低芯片动态功耗的有效方法。

Clock gating is a well - known technique to reduce dynamic power .