加法器

接着，在一维线性DNA自组装加法算法的基础上构造出DNA计算机加法器样机。

Then , a DNA adder prototype was constructed based on linear DNA self-assembly addition algorithm .

三数据通道浮点加法器的FPGA实现

The FPGA Implementation of the Triple Data-path Floating-point Adder

基于模块化结构的N位加法器的测试生成

Test Pattern Generation for Modular Structure Based N Bit Adders

针对单个stuck－at故障，研究了N位加法器的测试矢量生成问题。

Test Pattern generation for single stuck at fault in N bit adders is discussed .

浮点加法器IP核的VHDL设计

Design of Floating - Point Adder IP Core Using VHDL

在高性能微处理器和DSP处理器中，加法器的运算时间至关重要。

In high-performance microprocessors and DSP processor , the adder computing time is of the essence .

由于加法器是计算机中最基本的运算模块，研究者相继提出各种DNA加法算法。

As a basic computational module of computer , a number of DNA addition algorithms have been proposed in the literature .

本文利用基于模代数的三值通用逻辑门&Uk，设计了一位三值全加法器和全乘法器电路。

In this paper , one-bit ternary full-adder and full-multiplier are designed by using ternary universal-logic-gate-UkS based upon modular algebra .

一种采用改进Domino加法器的高速流水线乘法器

High Speed Pipelined Multiplier Using a Modified Domino Adder

低功耗超高速CMOS加法器设计研究

Low Power Ultra High Speed CMOS Adder

一种采用较少加法器的FIR滤波器实现方法

Realization of FIR Filter with Minimum Adders

DSP芯片中浮点加法器LOD电路的设计

A Design of LOD for DSP Floating-Point Adder

提出了两种改进型Domino加法器电路；

Two new modified Domino adders are proposed ;

在乘法器单元中采用BOOTH算法和先进进位加法器相结合的单元设计；

The multiplier unit adopts the BOOTH algorithm and carry lookahead adder ;

基于互补型单电子晶体管（SET）逻辑门，提出了SET加法器、移位寄存器和ROM的单元电路。

Based on logic gates of complementary single-electron transistor ( SET ), three units are proposed as follows : full adder , shift register and ROM.

介绍一种新型异步ACS（加法器-比较器-选择器）的设计。

A novel asynchronous ACS ( Add-Compare-Select ) is described .

以一个CCM加法器构件包装成EJB构件的实验验证了算法的可行性。

Validate the packaging algorithm with a practical instance .

实验证明，通过这种算法可得到运算速度高、电路结构简单的高速加法器。以满足数字信号处理（DSP）系统的高性能要求。

The design and simulation results of some addition circuits show that simple high speed adders can be obtained by the presented algorithms .

浮点加法器的VHDL算法设计

Design Arithmetic of Float Adder in VHDL

一种基于CSA加法器的Montgomery模幂乘硬件实现算法

A Montgomery modular multiplication hardware implementation algorithm based on CSAs

基于Verilog语言的循环式加法器的设计

The Design of a Circular Adder Based on Verilog HDL

这个结构只需要N-1个乘法器和N＋1个加法器。

Only N-1 multipliers and N + 1 adders are required .

针对加法器，对并行前缀结构进行了优化，将其与Ling进位和改进的选择进位模块相结合设计实现了一种新型的加法器。

Based on the optimized parallel-prefix formulation , Ling carry and modified carry-select module , a new adder is presented .

该乘加单元是通过对BOOTH型乘法器与高速加法器结构的深入研究而探索出来的。

Through studying BOOTH multiplier and high speed adder structures , we explored a new multipiler add unit .

用VHDL设计快速BCD码加法器

The Design of Rapid Adder Using VHDL

给出了处理器中异步加法器的电路结构，设计了一个采用Booth译码wallacetree结构的异步乘法器。

Circuits of asynchronous adder are proposed . An asynchronous multiplier using booth decode and based on Wallace tree architecture is designed .

给出了一种仅用加法器和移位器实现的、适用于嵌入式fpga应用的，可重构的∑-Δ调制器设计。

In this paper , a scheme of re-configurable Sigma-Delta Modulator ( SDM ) only using adders and shifters is advised , which is suitable for embedded FPGA applications .

浮点ALU中选择进位复合加法器的优化设计

Optimal Design of Carry-select Compound Adder in Floating-point ALU

该电路包括了用DDS产生的中心频率发生器、5对低通滤波器、20个乘法器和一个加法器。

This circuit include DDS which generate central frequency , five pair of low pass filter , 20 multipliers , and an adder .

加法器的设计采用了先进的并行前缀Hancarlson结构，对逻辑级数与扇出度进行了很好的折中。

Advanced Hybrid Prefix Adder Han Carlson structure is adopted in adder design which is a find trade-off between logic level and fan-out .