rtl

The IC design method base on RTL has been widely used .

集成电路设计在寄存器传输级的设计方法已经非常成熟。

Sequential logic synthesis is an important part of RTL synthesis system design .

时序逻辑综合是RTL综合系统设计中的一个重要部分。

Research on how to use tool to do RTL synthesis

怎样能更好地应用工具进行RTL综合研究

Realization of Sequential Logic Synthesis in RTL Synthesis System Design

RTL综合系统设计中时序逻辑综合的实现方法

Accelerating RTL Quality Assessment Method Based on CAD Tools

基于CAD工具的集成电路RTL质量快速评估方法

Test Method of DSP Chip RTL Based on XML

基于XML的DSP芯片RTL级测试方法

RTL 8019 AS and Its Application in Embedded Ethernet System

RTL8019AS及其在嵌入式以太网系统中的应用

Equivalence Checking between System Level Model and RTL Implementation

系统级模型与RTL实现的等价性验证方法

Application of single - chip microcomputer at network data transfer based on RTL 8019 AS

基于RTL8019AS单片机在网络数据传送中应用

Research on RTL Fault Models and Test Generation

集成电路寄存器传输级故障模型与测试生成研究

Fault Number Prediction and Fault Coverage Calculation in Pure RTL

完全RTL的故障数目预测及故障覆盖率计算

RTL test pattern generation algorithm based on CRG model

基于CRG模型的RTL测试矢量生成算法

( 4 ) giving the set of the general RTL components ;

给出RTL通用元件集；

The RTL design of the module is completed using Verilog .

针对该芯片的架构，提出了缓冲器管理单元的设计方案，并应用Verilog语言完成了该单元的RTL级设计。

Automatically Extracting Sequential Information of Integrate Circuits Based on RTL

自动提取RTL级集成电路时序信息

Variable Assignment Statement Synthesis M Variable Assignment Statement Synthesis Method in RTL Synthesis

RTL综合中变量赋值语句的综合方法

Warrants for RTL are analyzed in view of safety and traffic operation efficiency .

从安全和交通效率两个方面研究左转相位的设置。

Finally , the RTL will be handed to the back end .

最后把RTL中间表示交给GCC后端进一步处理。

The two algorithms generate tests for RTL circuits by test sets for modules .

这两个算法主要通过对电路按结构、功能划分为功能模块，然后利用功能模块的测试集进行RTL电路测试产生。

In the logical design , an IP RTL description and function simulation are completed .

在逻辑设计中，完成了IP的RTL级的功能描述、功能仿真以及逻辑综合。

Optimization of Architecture for Viterbi Decoder on RTL Design Stage

Viterbi解码器RTL级设计优化

RTL Property Checking Based on Linear Programming

基于线性规划的RTL性质验证研究

Study On a High-Level Synthesis-Based RTL Synthesis Object and Its Methods

基于高级综合的RTL综合对象及方法的研究

Delay Test Generation for Processors Combining RTL and Gate Level Netlist

RTL和门级结合的处理器时延测试产生方法

Reuse of the Controler Synthesis Technology in the Implementation of RTL Synthesis

重用控制器综合技术实现RTL综合

An effective logic transform for the finite automaton RTL description

有限自动机RTL描述的一种有效逻辑转换

RTL Low Power Design Methodology

寄存器传输级低功耗设计方法

RTL Object Types and Classes Analysis

RTL对象类型和分类浅析

After design of the RTL level , simulation is made on esch module .

设计完成后，对各模块进行了仿真。

Traditional RTL design is not able to handle the complex SoC because of slow simulation speed .

传统的RTL级设计由于对系统的抽象不够，不能有效处理复杂的SoC系统，在RTL级的仿真性能不能满足需要。