maxplus

1

Use stratification construct and BUS to design logic functional diagram ane imitate it on MAXPLUS ⅱ platform of EDA ;

在EDA的MAXPLUSⅡ平台上利用层次化结构和BUS总线，设计4位十进制数字密码锁的逻辑功能图并仿真；
2

This paper discusses some general problems about optimum of area in using VHDL , Through the experiences that use the VHDL to program on Maxplus ⅱ system , and gives some examples .

根据应用MaxplusⅡ软件进行VHDL语言代码编写的经验，结合相应实例，阐述有关VHDL编码方面的面积优化问题。
3

Using " Maxplus ⅱ", a famous EDA development tool to edit , compile , synthesize and download to CPLD device , practical circuit testing shows that the system is running well .

利用EDA开发工具MaxplusⅡ对该项目进行编辑、编译、综合和仿真，并下载到CPLD器件中，经实际电路测试，运行良好。